FinFETs are three dimensional structures which provide excellent scalability. For example, FinFETs rise above the planar substrate, giving them more effective gate width for the same substrate footprint than conventional gate structures. Also, by wrapping the gate around the channel, the FET is fully depleted, so that little current is allowed to leak through the body when the device is in the off state, i.e., thereby providing low gate leakage current. This provides superior performance characteristics, e.g., high on currents due to the larger effective gate width, lower off currents due to the full depletion and less threshold voltage variations due to lower channel doping, resulting in improved switching speeds and power.
FinFETs can be fabricated using, for example, silicon on insulator (SOI) substrates. In SOI technologies, FinFETs can be used with many other devices and structures, and can be fabricated using CMOS technologies, e.g., lithography, etching and deposition methods. However because of the three dimensional structure, integration with other devices and/or structures are difficult and quite challenging. For example, it is a challenge to fabricate deep trench capacitors (eDRAM) with current FinFET fabrication processes.